This invention relates to an integrated circuit (IC) assembly that permits a user to monitor and control a parameter at the core of the IC.
Programmable logic devices (PLDS) are user configurable integrated circuits (ICs) that implement digital logic functions. Field programmable gate arrays (FPGAs), one type of PLD, typically include configurable logic blocks (CLBs), input/output (I/O) blocks, and a programmable routing matrix for interconnecting the CLBs and I/O blocks. FPGAs, in general, are described in U.S. Pat. No. Re 34,363, reissued on Aug. 31, 1993 and incorporated by reference herein.
In the Virtex(trademark) family of FPGAs, the programmable routing matrix provides five types of routing resources. xe2x80x9cThe 1999 Xilinx Programmable Logic Data Bookxe2x80x9d, pages 3-10 to 3-12. The first type of routing resource, local routing, is used for interconnecting elements within each CLB and horizontally adjacent CLBs. The second type of routing resource, general purpose routing, is located in the horizontal and vertical routing channels associated with the rows and columns of CLBs. General purpose routing includes general routing matrices (GRMs) that provide CLBs access to the general purpose routing, single-length lines that connect adjacent GRMs, buffered Hex lines that connect GRMs six blocks away, and long lines that distribute signals across the FPGA. The third type of routing resource, I/O routing, provides an interface between the CLB array and the I/O blocks. The fourth type of routing resource, dedicated routing, is provided for on-chip tristate buses and for carry signals. In the Virtex FPGA, four partitionable tristate bus lines are provided for each CLB row and two nets per CLB propagate carry signals vertically to the adjacent CLB. Finally, the fifth type of routing resource, global routing, distributes clocks and other signals having high fanout throughout the device. Primary global routing includes four dedicated global nets for distributing clock signals. Secondary global routing includes 24 backbone lines, 12 lines at the top of the chip and 12 lines at the bottom, that can distribute clock or non-clock signals.
Other families of FPGAs provide different routing resources as well as different CLB and I/O block elements. Other types of PLDs, such as complex programmable logic devices (CPLDs), also vary significantly in architecture.
Due to the programmability of function generators, I/O blocks, and routing resources, PLDs have a wide range of power consumption. Moreover, typically because of system constraints, PLDs must also operate under a wide range of frequencies, which also affects their power consumption. Finally, as PLDs are being designed with reduced process geometries, PLDs have lower operating voltages, thereby also affecting their power consumption.
A PLD assembly typically experiences a voltage drop due to the resistances of its various components. Ohm""s Law states that a voltage is equal to the product of the current flowing through a component and that component""s resistance (V=Ixc3x97R). Therefore, as current flow increases in the PLD, the voltage drop experienced in the PLD assembly increases proportionally. As a result, the voltage applied at the core of the IC die in the PLD assembly can be significantly lower than the supply voltage. Moreover, with the trend toward lower supply voltages, there is very little margin for voltage drop before reduced performance and/or functional errors may occur at the core of the IC die.
To address these concerns, those skilled in the art have proposed several solutions. For example, one typical solution is to provide a voltage regulator at a location on the printed circuit board (PCB) that is central to its destination ICs. In this manner, the resistive path to the PLD is reduced and any voltage drop on the path is minimized. Occasionally, centralized voltage regulators also use a sensor point located on the PCB to regulate voltage at that localized point. With such solutions, however, the voltage drop of the PLD itself is not monitored or reduced.
Another proposed solution is to add more power pins to the PLD, thereby reducing the effective resistance of resistive paths within the PLD. However, with increased functionality requirements, many PLDs are already pad limited. Therefore, the advantage of a possible reduced voltage drop is more than offset by the significant disadvantage of reduced input/output connectivity.
Therefore, a need has arisen for a structure and method that can accurately monitor the voltage at a particular location on the PLD as well as compensate for a voltage drop on the PLD, all without significantly affecting input/output connectivity.
The present invention addresses these problems by adding a sensor point on an integrated circuit (IC) die. In one embodiment, the sensor point is centrally located on the IC die and a dedicated sensor trace connects the sensor point to one of a plurality of input/output (I/O) structures located at the periphery of the IC die. A power bond wire connects that I/O structure to a dedicated voltage sensor pin provided on the IC""s package.
In this manner, the end user can accurately monitor the voltage at the sensor point on the IC die. This information can then be advantageously used to regulate the power supply on the IC die. Specifically, if the voltage is deviating from an acceptable range, the end user can provide a different external voltage, thereby ensuring a proper internal operating voltage on the IC die.
Moreover, information from the sensor point can also be used to improve various engineering features including circuit architecture, packaging, printed circuit board design, and other design areas. Additionally, information from the sensor point can be used to control secondary system parameters, such as clock speed, fan speed, software routines, and IC programming.